Stacked double sided integrated circuit package
US6274929A · kind A · utility
22Cited by
26References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Sep 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.