Semiconductor wafer, a chemical-mechanical alignment mark, and an apparatus for improving alignment for metal masking in conjunction with oxide and tungsten CMP
US6274940A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1999 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Jul 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.