Multiple byte channel hot electron programming using ramped gate and source bias voltage
US6275415A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 1999 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Oct 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated. In another embodiment, a bias voltage is applied to the common source terminal and a bias voltage is applied to the common well voltage. The combination of the voltages applied to the control gates and to the sources decreases loading on the bitlines to ensure that V.sub.DS does not fall be…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.