Synchronous integrated memory
US6275445A · kind A · utility
6Cited by
5References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2000 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Jul 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has data lines through which data connections are connected to groups of memory cells via a synchronizing unit. The synchronizing unit is disposed adjacent to the cell group and has a clock input to which an internal clock signal is fed. In the event of a write access to the memory, the synchronizing unit synchronizes with the internal clock signal data signals that are fed via the data connections and are synchronous with an external clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.