Method of forming vertical planar DMOSFET with self-aligned contact

US6277695A · kind A · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Richard K. Williams · Cupertino, US
• Sung-Shan Tai · San Jose, US
• Dorman C. Pitzer · San Jose, US
• Wayne B. Grabowski · Los Altos, US
• Anthony C. Tsui · Saratoga, US
• Mike F. Chang · Cupertino, US

Key dates

• Filing date: Apr 16, 1999
• Grant date: Aug 21, 2001
• Expiry date: Apr 16, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/665

Abstract

The metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET. With the metal contact self-aligned to the gate in this way, the lateral dimension of each of the cells in the DMOSFET can be significantly reduced without the risk of a short between the contact and the gate, and the packing density of the cells can be increased. In this way, significant reductions in the on-resistance of the device can be achieved.