Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill

US6281082A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Feng Chen · Singapore, SG
• Kok Hin Teo · Singapore, SG
• Kok Hiang Tang · Singapore, SG
• Alex See · Singapore, SG

Key dates

• Filing date: Mar 13, 2000
• Grant date: Aug 28, 2001
• Expiry date: Mar 13, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76237
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A new method of forming MOS transistors in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A pad oxide layer is deposited. A silicon nitride layer is deposited. Trenches are patterned for planned shallow trench isolations. The sidewalls of the trenches are oxidized. A photoresist layer is deposited overlying the silicon nitride layer and filling the trenches. The photoresist layer is etched down to below the top surface of the silicon nitride layer. The silicon nitride layer is patterned to form dummy gate electrodes. Sidewall spacers are formed on the dummy gate electrodes. The photoresist layer is removed. A dielectric layer is deposited overlying the dummy gate electrodes and the trenches. The dielectric layer is polished down to the top surface of the dummy gate electrodes to thereby complete the STI and the ILD. The dummy gate electrodes are etched away. A gate oxide layer is formed. A gate electrode layer is deposited overlying the dielectric layer and filling the openings for the planned transistor gates. The gate electrode layer is polished down to form the transistor gates, and the integrated circuit is completed.