Patent · US Expired

Integrated circuit for generating a phase-shifted output clock signal from a clock signal

US6285228A · kind A · utility

8Cited by

3References

7Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Patrick Heyne · Hersbruck, DE
Thomas Hein · Hersbruck, DE
Torsten Partsch · San Jose, US
Thilo Marx · Villingen-Schwenningen, DE

Key dates

Filing date	Jun 29, 2000
Grant date	Sep 4, 2001
Priority date	—
Expiry date	Jun 29, 2020

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00019
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The integrated circuit generates an output clock signal with a phase shift relative to a first clock signal. The currents I.sub.E =I.sub.1 and I.sub.L =I.sub.2 can be weighted differently by means of control signals. A different phase shift of the output clock signal results depending on the weighting.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.