Method for fabricating graded LDD transistor using controlled polysilicon gate profile
US6287922A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1998 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Sep 28, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/978
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer, forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.