Method of defining copper seed layer for selective electroless plating processing
US6287968A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1999 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Jan 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76879
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing semiconductor wafers using electroless plating processing. A partially completed semiconductor wafer having trenches and vias formed in a layer of interlayer dielectric has a barrier layer globally formed on the surface of the partially completed semiconductor wafer. A seed layer is globally formed on the surface of the barrier layer. The barrier and seed layers are removed from portions of the surface of the partially completed semiconductor wafer on which plating is not to occur. The partially completed semiconductor wafer is then subjected to an electroless plating process and conductive material is plated on those portions of the seed layer that remains on the partially completed semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.