Self-aligned contact for closely spaced transistors

US6294449A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Teresa J. Wu · Rexford, US
• Bomy Chen · Cupertino, US
• John W. Golz · Manassas, US
• Charles W. Koburger, III · Delmar, US
• Paul C. Parries · Wappingers Falls, US
• Christopher J. Waskiewicz · Rexford, US
• Jin J. Wu · Hopewell Junction, US

Key dates

• Filing date: Nov 23, 1999
• Grant date: Sep 25, 2001
• Expiry date: Nov 23, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76897
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.