Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming

US6306777A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Robert B. Ogle · San Jose, US
• Arvind Halliyal · Cupertino, US

Key dates

• Filing date: Jun 15, 2000
• Grant date: Oct 23, 2001
• Expiry date: Jun 15, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A flash memory structure and fabrication process whereby stacks of a first poly-crystalline or of an amorphous silicon material (polysilicon), having a bottom layer member of an interpoly dielectric stack, are processed for formation of a post-treatment layer over the bottom interpoly dielectric layer member. The post-treatment layer is essentially a solid material formed by a chemical reaction for purposes of improving the reliability of an interpoly dielectric stack and results in changes to the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The post-treatment layer is formed by exposing the polysilicon stacks with the bottom interpoly dielectric layer member to a selected one of at least three ambient reagent gases. The selected ambient reagent gases and exposure of the semiconductor structure being performed in either a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber. Then at least three ambient reagent gases are selected from a group of reagent gases consisting essentially of N.sub.2 O/NO, O.sub.2 /H.sub.2 O/O.sub.3, and NH.sub.3 /N.sub.2. Any of the ambient reagent gases may be…