Negative gate erase
US6307784A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Oct 23, 2001 |
| Priority date | — |
| Expiry date | Feb 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. After the first erase pulse, the erase verify routine can be performed on all the IO's together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage and the value of Vgate voltage is at a substantially high negative voltage where the voltage potential between Vdrain and Vgate is also a substantially high voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.