Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials
US6312874A · kind A · utility
38Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1998 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Nov 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0332
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a dual damascene structure in low k dielectric material employs a multiple layer hard mask over the low k dielectric layer. The trench pattern is etched into the hard mask layer, followed by etching of a via pattern. The trench pattern is widened to completely coincide with the via if the via does not fall completely within the trench pattern due to alignment errors. The low dielectric constant material is protected from the photoresist removal process during the patterning and initial formation of the trench and via in the multiple layer hard mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.