Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device
US6319775A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1999 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Oct 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/022
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a nitrogenated top oxide layer. The process includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. After forming the top oxide layer, an annealing process is carried out to diffuse nitrogen into the top oxide layer. The formation of a nitrogenated top oxide layer provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.