High k interconnect de-coupling capacitor with damascene process
US6323099A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2000 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Feb 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
An integrated circuit (IC) including integral, high k dielectric de-coupling capacitor constructed using a damascene process and contained within a single conductive layer of the IC structure. The IC comprises a substrate, a dielectric layer disposed over the substrate, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first line disposed adjacent to a second line, and a high k dielectric material disposed between the first line and the second line. The capacitor is formed between the first line and the second line separated by the high k dielectric material. Coupling the first line to a signal and coupling the second line to a capacitor signal connects the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.