Method for fabricating a semiconductor device having different gate oxide layers
US6329249A · kind A · utility
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12Claims
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Key dates
| Filing date | Jun 15, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Jun 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method for fabricating a semiconductor device with different gate oxide layers. Oxidation is controlled in accordance with the active area dimension so that oxide grows thin at a wider active width (peripheral region) and grows thickly at a narrower active width (cell array region). A gate pattern is formed on a semiconductor substrate having different active areas. Gate spacers are formed and then active dimension dependent oxidation process is performed to grow the oxide layers differently from one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.