High reliability lead frame and packaging technology containing the same
US6331728A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1999 |
| Grant date | Dec 18, 2001 |
| Priority date | — |
| Expiry date | Feb 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lead frame includes a first side rail, a second side rail spaced apart from the first side rail, a center rail disposed between the first side rail and the second side rail, and a plurality of package locations. Each package location includes a first and a second die attach paddle. The first die attach paddle supports a first side of a semiconductor die and is coupled only to the first side rail or to the second side rail. The second die attach paddle supports a second side of the semiconductor die and is coupled only to the center rail. The first and second die attach paddles are separate and unconnected to each other and may be generally circular in shape. An aggregate surface area of the first and second paddles may be less than about 25 percent of a surface area of the semiconductor die. By limiting the surface area of the interfaces between the lead frame and the silicon die and the surface area of the interfaces between the lead frame and the molding compound, moisture-related problems and problems related to the differing coefficients of thermal expansion (such as delamination and/or cracks, for example) of the constituent materials of the resultant semiconductor device ar…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.