Positive gate erasure for non-volatile memory cells
US6331952A · kind A · utility
11Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2000 |
| Grant date | Dec 18, 2001 |
| Priority date | — |
| Expiry date | Oct 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes simultaneously applying a first positive voltage across the gate and a second positive voltage to the first region, wherein the second positive voltage is greater than the first positive voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.