Intelligent ramped gate and ramped drain erasure for non-volatile memory cells
US6331953A · kind A · utility
18Cited by
1References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2000 |
| Grant date | Dec 18, 2001 |
| Priority date | — |
| Expiry date | Oct 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/691
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes: applying a voltage across the gate and the first region in accordance with a coarse erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region; and applying a voltage across the gate and the first region in accordance with a fine erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.