Method of producing a vertical MOS transistor

US6337247B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thomas Schulz · Austin, US
• Thomas Äugle · Birkenfeld, DE
• Wolfgang Rosner · Hersbruck, DE
• Lothar Risch · Neubiberg, DE

Key dates

• Filing date: Jan 18, 2000
• Grant date: Jan 8, 2002
• Expiry date: Jan 18, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/63

Abstract

A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantation. The second source/drain region is self-aligned on two mutually opposite flanks of the layer structure. A gate electrode can be produced in the form of a spacer on the two flanks. In order to avoid a capacitance formed by a first contact of the gate electrode and the first source/drain region, a part of the first source/drain region may be removed. If the layer structure is produced along edges of an inner area, then a third contact of the second source/drain region may be produced inside the inner area in order to reduce the surface area of the transistor.