Removable spacer technology using ion implantation for forming asymmetric MOS transistors
US6344396B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2000 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | Sep 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
Sub-micron-dimensioned, asymmetrically-configured MOS and/or CMOS transistors are fabricated using removable sidewall spacers made of a material, such as UV-nitride, one of which is selectively treated subsequent to deposition, e.g., by ion implantation, to augment the etch rate thereof with a room temperature etchant, e.g., dilute aqueous HF. The treated spacer is removed with the dilute, aqueous HF prior to implantation of asymmetrically-configured, moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.