Simplified graded LDD transistor using controlled polysilicon gate profile
US6350639B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2001 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Apr 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.