Patent · US Expired

Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same

US6352885B1 · kind B1 · utility

19Cited by

14References

22Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Karsten Wieczorek · Dresden, DE
Frederick N. Hause · Austin, US
Manfred Horstmann · Dresden, DE

Key dates

Filing date	May 25, 2000
Grant date	Mar 5, 2002
Priority date	—
Expiry date	May 25, 2020

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10S438/981
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A transistor having a gate insulation layer whose peripheral portion has an increased thickness and a method of fabricating these transistor devices is disclosed. The peripheral portions with increased thickness of the gate insulation layer significantly reduce the injection of charge carriers into the gate insulation layer. Accordingly, the transistors described in the present application exhibit an improved long-time reliability. In addition, the lateral penetration of ions beneath the gate insulation layer for forming the lightly-doped drain and/or the lightly doped source is increased since the implantation may be performed at a tilt angle with respect to the perpendicular direction which is the conventionally used direction of the implantation step.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.