Patent · US Expired

Integrated semiconductor memory with redundant units for memory cells

US6353562B2 · kind B2 · utility

35Cited by

4References

9Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Böhm · Zorneding, DE
Heinz Honigschmid · Starnberg, DE
Stefan Lammers · Hersbruck, DE
Zoltan Manyoki · Gatineau, CA

Key dates

Filing date	Feb 9, 2001
Grant date	Mar 5, 2002
Priority date	—
Expiry date	Feb 9, 2021

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/787
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.