Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure
US6356482B1 · kind B1 · utility
31Cited by
9References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 7, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Sep 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure having charge stored near both the source and drain. During the erase operation, a negative gate erase voltage is applied along with a positive source and drain voltage to improve the speed of erase operations and performance of the non-volatile memory cell after many program-erase cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.