Method to form damascene interconnects with sidewall passivation to protect organic dielectrics

US6358842B1 · kind B1 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Mei Sheng Zhou · Singapore, SG
• Simon Chooi · Singapore, SG
• Yi Xu · Singapore, SG

Key dates

• Filing date: Aug 7, 2000
• Grant date: Mar 19, 2002
• Expiry date: Aug 7, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76808
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors. A copper layer is deposited overlying the capping layer and filling the via openings. The copper layer is polished down to complete the damascene interconnects in the manufacture of the integrated circuit device.