Flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same
US6359342B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2000 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Dec 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip-chip bumping technology is proposed, which provides a flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same. The proposed flip-chip bumping technology is characterized by the forming of a lined-array of electrically-conductive dual-pad blocks respectively over the internal I/O points of the semiconductor chip, each dual-pad block including a first pad and a second pad located beside and electrically connected to the first pad; and wherein the respective first and second pads of the dual-pad blocks-are alternately designated as bump pads and test pads. During testing procedure, the probing to the internal circuitry of the semiconductor chip is carried out through the test-pad portions of the dual-pad blocks, so that the probing needles would leave no scratches over the bumppad portions of the same. During subsequent bumping process, solder bumps are formed respectively over the bump-pad portions of the dual-pad blocks. Since the bump-pad portions of the dual-pad blocks would be left unscratched, it allows the solder bump attachment to be more assured in quality and reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.