DRAM cell circuit

US6362502B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Wolfgang Rosner · Hersbruck, DE
• Thomas Schulz · Austin, US
• Lothar Risch · Neubiberg, DE
• Franz Hofmann · Munich, DE

Key dates

• Filing date: Oct 19, 2000
• Grant date: Mar 26, 2002
• Expiry date: Oct 19, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/053

Abstract

A memory cell contains a memory transistor and a transfer transistor. A gate electrode of the transfer transistor and a control gate electrode of the memory transistor are connected to a word line. The memory transistor has a floating gate electrode that is isolated from a channel region of the memory transistor by a first dielectric layer and is connected to a first source/drain region of the transfer transistor. The control gate electrode is isolated from the floating gate electrode by a second dielectric layer. A first source/drain region of the memory transistor is connected to a bit line. The memory and transfer transistors are preferably of different conductivity types. During the writing of information, the transfer transistor is in the on-state and the memory transistor is in the off-state. During the reading-out of information, the transfer transistor is in the off-state and the memory transistor is in the on-state.