Flash memory process using polysilicon spacers
US6365455B1 · kind B1 · utility
10Cited by
14References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1998 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Jun 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0411
Abstract
An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.