Method for producing PMOS devices
US6365471B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1999 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Jun 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
A method for preventing boron segregation and out diffusion to form PMOS devices is disclosed. The method includes providing a semiconductor substrates and the formation of a gate oxider layer as well as a gate layer on top of the semiconductor substrate. Next, a photoresist layer is formed on a top surface of the gate layer, moreover, a pattern is transferred onto the photoresist layer after being put through an exposure and a development. Furthermore, the gate layer and the oxide layer are then etched using the photoresist layer as a mask, and the photoresist layer is removed afterward. In succession, a thin silicon nitride layer is grown utilizing RTCVD processing. Thereafter, high doped drain regions of boron ion shallow junctions are formed by carrying out ion implantation. A silicon oxide layer is deposited using LPCVD, and forming spacers by etching the silicon oxide layer. Next, a heavy doping of boron ions proceeds, as well as an annealing process. The thin silicon nitride layer is etched using diluted phosphoric acid solution. The final stage is the formulation of metal silicides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.