Patent · US Expired

Circuit configuration for generating an output clock signal with optimized signal generation time

US6366527B2 · kind B2 · utility

5Cited by

4References

8Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Hein · Hersbruck, DE
Thilo Marx · Villingen-Schwenningen, DE
Patrick Heyne · Hersbruck, DE
Torsten Partsch · San Jose, US

Key dates

Filing date	Jan 31, 2001
Grant date	Apr 2, 2002
Priority date	—
Expiry date	Jan 31, 2021

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/22
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

DDR SDRAM memory chips require a highly precise output clock signal in order to pass the stored data onto a data highway at the correct instant. This signal is generated by a symmetrical circuit configuration that, by virtue of the integration of a multiplexer in a clock ratio compensator, additionally generates the output clock signal in a minimal time.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.