Method of copper interconnect formation using atomic layer copper deposition
US6368954B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 28, 2000 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Sep 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1089
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor interconnect structure having a substrate with an interconnect structure patterned thereon, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer. A process for creating such structures is described. The barrier layer is formed using atomic layer deposition techniques. Subsequently, a pre-seed layer is formed to create a heteroepitaxial interface between the barrier and pre-seed layers. This is accomplished using atomic layer epitaxy techniques to form the pre-seed layer. Thereafter, a seed layer is formed by standard deposition techniques to create a homoepitaxial interface between the seed and pre-seed layers. Upon this layered structure further bulk deposition of conducting materials is done. Excess material is removed from the bulk layer and a sealing layer is formed on top to complete the interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.