Semiconductor integrated circuit device and method for production of the same
US6372554B1 · kind B1 · utility
77Cited by
6References
21Claims
0Family size
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Inventors
Key dates
| Filing date | Sep 7, 1999 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Sep 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A pattern of more than one conductive layer overlying a fuse formed in a TEG region is subject to OR processing; further, a combined or “synthetic” pattern with an opening pattern of one or more testing pads connected to said fuse added thereto is copied by transfer printing techniques to a photosensitive resin layer that is coated on the surface of a semiconductor wafer, thereby forcing the resin layer to reside only in a selected area of a scribe region, to which area the synthetic pattern has been transferred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.