Integrated capacitor on the back of a chip
US6373127B1 · kind B1 · utility
204Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1999 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Sep 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is disclosed. The device includes an integrated circuit chip having integral de-coupling capacitors on the chip backside. The de-coupling capacitors includes a metal layer in intimate contact with the semiconductor substrate of the integrated circuit, a dielectric layer and a second metal layer. The second metal layer is segmented to form multiple capacitors, and each capacitor is interconnected to power supplies of the chip. Interconnection to different integrated circuit packages is provided. A method of making the semiconductor device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.