Patent · US Expired

Semiconductor wafer alignment using backside illumination

US6376329B1 · kind B1 · utility

34Cited by
3References
13Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 4, 1997
Grant dateApr 23, 2002
Priority date—
Expiry dateAug 4, 2017

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG03F9/7084
  • WIPO fieldOptics
  • WIPO sectorInstruments

Abstract

A projection exposure apparatus for exposing a semiconductor wafer to a pattern, formed on a reticle, using a projection lens system. An alignment optical system is disposed at a backside of the wafer which is remote from the projection lens system. The alignment optical system detects an alignment mark provided on the frontside of the wafer from the backside of the wafer. Thus the wafer alignment mark is detected without being adversely affected by integrated circuit layers, e.g. photoresist, metallization, etc. applied to the principal surface (frontside) of the wafer, and the reticle and wafer can be aligned accurately. Any tilting or wedging of the wafer, i.e. non-normality to the incident light beam, is detected and corrected for.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.