Method to prevent CU dishing during damascene formation
US6376376B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2001 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Jan 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method of copper damascene metallization utilizing an additional oxide layer between the nitride and the barrier layers to prevent dishing of the copper line after CMP is described. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. A polish stop layer is deposited overlying the insulating layer. An oxide layer is deposited overlying the polish stop layer. An opening is etched through the oxide layer, the polish stop layer, and the insulating layer to one of the semiconductor device structures. A barrier metal layer is deposited over the surface of the oxide layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and the barrier metal layer not within the opening are polished away wherein the barrier metal layer polishes more slowly than the copper layer whereby dishing of the copper layer occurs. Thereafter, the oxide layer is polished away stopping at the polish stop layer wherein the oxide layer polishes more quickly than the copper layer whereby the dishing of the copper layer is removed and whereby a hump is formed on the copper layer after the oxide…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.