Wang Ling Goh
18Patents
8h-index
25Co-inventors
64Inventor score
Filing activity: Oct 2, 2000 → Aug 21, 2006
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6376376B1 | Method to prevent CU dishing during damascene formation | Electricity | 43 | Expired |
| US6841847B2 | 3-D spiral stacked inductor on semiconductor material | Emerging Cross-Sectional Technologies | 34 | Expired |
| US6558994B2 | Dual silicon-on-insulator device wafer die | Emerging Cross-Sectional Technologies | 31 | Expired |
| US6380084B1 | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling | Electricity | 27 | Expired |
| US6613652B2 | Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance | Electricity | 20 | Expired |
| US6403484B1 | Method to achieve STI planarization | Electricity | 11 | Expired |
| US6613649B2 | Method for buffer STI scheme with a hard mask layer as an oxidation barrier | Electricity | 8 | Expired |
| US6468880B1 | Method for fabricating complementary silicon on insulator devices using wafer bonding | Emerging Cross-Sectional Technologies | 8 | Expired |
| US7119010B2 | Integrated circuit with self-aligned line and via and manufacturing method therefor | Electricity | 6 | Expired |
| US6849928B2 | Dual silicon-on-insulator device wafer die | Emerging Cross-Sectional Technologies | 5 | Expired |
| US6998682B2 | Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension | Electricity | 5 | Expired |
| US6905919B2 | Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension | Electricity | 4 | Expired |
| US7721414B2 | Method of manufacturing 3-D spiral stacked inductor on semiconductor material | Emerging Cross-Sectional Technologies | 4 | Active |
| US6613648B1 | Shallow trench isolation using TEOS cap and polysilicon pullback | Electricity | 2 | Expired |
| US7060573B2 | Extended poly buffer STI scheme | Electricity | 1 | Expired |
| US8766454B2 | Integrated circuit with self-aligned line and via | Electricity | 1 | Active |
| US6399471B1 | Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application | Electricity | 1 | Expired |
| US6472697B2 | Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.