Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor
US6376877B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Feb 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A reduced device geometry and increased device efficiency semiconductor memory device is provided. The method of manufacturing the semiconductor memory device includes forming shallow trench isolations (STIs) on the semiconductor substrate, forming a photoresist mask over the STIs, selectively etching the STIs to form curved surface area profiles, growing a layer of tunnel oxide (TOX) over exposed areas of the semiconductor substrate, forming a first polysilicon (poly) layer over the TOX layer and the STIs, chemical-mechanical polishing (CMP) the first poly layer, forming an oxide-nitride-oxide (ONO) layer over the first poly layer, and forming a second poly layer over the ONO layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.