Method of manufacturing a transistor with local insulator structure
US6380019B1 · kind B1 · utility
138Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1998 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Nov 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.