High-speed semiconductor transistor and selective absorption process forming same
US6380044B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Apr 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-speed semiconductor transistor and process for forming same. The process includes forming, in a Si substrate (10), spaced apart shallow trench isolations (STIs) (20), and a gate (36) atop the substrate between the STIs. Then, regions (40,44) of the substrate on either side of the gate are either amorphized and doped, or just doped. In certain embodiments of the invention, extension regions (60,62 or 60′,62′) and deep drain and deep source regions (80, 84 or 80′,84′) are formed. In other embodiments, just deep drain and deep source regions (80, 84 or 80′, 84′) are formed. A conformal layer (106) is then formed atop the substrate, covering the substrate surface (11) and the gate. The conformal layer can serve to absorb light and/or to distribute heat to the underlying structures. Then, at least one of front-side irradiation (110) and back-side irradiation (116) is performed to activate the drain and source regions and, if present, the extensions. Explosive recrystallization (124) is one mechanism used to achieve dopant activation. A deep dopant region (120) may be formed deep in the substrate to absorb light and release energy in the form of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.