Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure
US6380556B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Jul 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.