Method of utilizing fast chip erase to screen endurance rejects
US6381550B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 1999 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of utilizing Fast Chip Erase to screen endurance rejects. Multiple sectors in a device are selected and a time necessary to program all cells in the sectors is monitored and if the monitored time exceeds a first time, the device fails. A time necessary to erase all the cells without any overerased cells is monitored and if the time exceeds a second time, the device fails. A time necessary to correct overerased cells is monitored and if the time exceeds a third time, the device fails. The total time from erase until overerase correction is achieved is monitored and if the total time exceeds a fourth time, the device fails. The total time to determine erasability is monitored and if this time exceeds a fifth time, the device fails.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.