Copper vias in low-k technology
US6383929B1 · kind B1 · utility
10Cited by
2References
5Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jan 11, 2001 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Jan 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.