Flash memory cell for high efficiency programming
US6384447B2 · kind B2 · utility
36Cited by
17References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2001 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Aug 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.