Method and system for controlling test data volume in deterministic test pattern generation
US6385750B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 1999 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Sep 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31813
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system for improving the fault coverage of test vectors for testing integrated circuits. The present invention also provides a method and system for reducing the number of deterministic test vectors required for testing integrated circuits by inserting test points in a cost effective manner. According to an embodiment of the present invention, a fault list having all the potential faults of an integrated circuit design is initialized and all the potential faults are marked as untestable. A set of test patterns, T, for testing several of the potential faults are generated. A fault simulation process is then performed on the integrated circuit design with the test patterns, T, to mark off untested faults. During fault simulation, fault propagation is monitored to determine the nets in the design to which faults were propagated. The nets at which fault propagation discontinues (e.g., de-sensitized) are also monitored. This information is collected over the set of test patterns, T. Based on the fault propagation information, test points are selectively inserted to maximize the fault coverage of the set of test patterns, T. In one embodiment, the nets to which most untested…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.