Process for manufacturing semiconductor integrated circuit device
US6387744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2001 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Mar 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.