Method of forming an on-chip decoupling capacitor with bottom hardmask
US6387754B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 22, 2001 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Jun 22, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.