Structure and process flow for fabrication of dual gate floating body integrated MOS transistors

US6392271B1 · kind B1 · utility

Assignee

• Intel Corporation · US

Inventors

• Mohsen Alavi · Portland, US
• Ebrahim Andideh · Portland, US
• Scott Thompson · Portland, US
• Mark Bohr · Beaverton, US

Key dates

• Filing date: Jun 28, 1999
• Grant date: May 21, 2002
• Expiry date: Jun 28, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/711

Abstract

A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer sited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.