Circuit configuration for generating a reference voltage for reading a ferroelectric memory
US6392918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2001 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Mar 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.