Test structures for electrical linewidth measurement and processes for their formation
US6399401B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jul 24, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/887
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of determining a linewidth of a polysilicon line formed by a lithographic process, a polysilicon layer is formed on a substrate. A line is patterned from said polysilicon layer using said lithographic process and a Van der Pauw structure is patterned from said polysilicon layer. N2 is then implanted into the polysilicon line and the polysilicon Van der Pauw structure to form a depletion barrier. A P-type dopant is the implanted into the polysilicon line and the polysilicon Van der Pauw structure and the dopant is activated. A sheet resistivity of the Van der Pauw structure is determined, and the linewidth of the polysilicon line is then determined by electrical linewidth measurement using the sheet resistivity of the Van der Pauw structure as the sheet resistivity of the polysilicon line. A related test structure is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.